1. Field of the Invention
The present invention relates to a clock generation circuit and a system including the same, and more particularly to a clock generation circuit generating a dock signal having a duty ratio that can be set or controlled, and a system including the clock generation circuit.
2. Description of the Background Art
In an LSI (Large Scale Integration) or a system using an LSI, clock signals are important signals that are required for synchronization with internal elements, internal modules or external devices. Internal elements, internal modules or external devices perform operations or communications in synchronization with rising edges or falling edges of clock signals.
In a conventional clock generation circuit generating a clock signal, the duty ratio of the clock signal is fixed, for example, at 50%.
When a workload of a circuit receiving a clock signal is different between an H (logic high) level duration and an L (logic low) level duration, the operational frequency of the circuit is determined in accordance with the period of time during which the workload is heavier, thereby decreasing the operational efficiency. Moreover, in this case, the power consumption is abruptly increased when the frequency of the clock signal is higher than a certain level.
In addition, when there are a plurality of circuits receiving clock signals, the current peaks occur at the same timing, resulting in increased noises due to EMI (Electromagnetic Interference) or the like.
In order to solve the aforementioned problems, for example, a duty ratio of a clock signal may be varied. Japanese Patent Laying-Open Nos. 6-164379 and 62-42613 disclose means for varying a duty ratio of a clock signal.
The conventional clock generation circuit disclosed in Japanese Patent Laying-Open No. 6-164379 includes a phase comparator and a frequency controlled voltage generation portion receiving an output of the phase comparator, wherein the duty ratio of the frequency can be arbitrarily set by a capacitance charge/discharge current.
The conventional clock generation circuit disclosed in Japanese Patent Laying-Open No. 62-42613 uses a delay circuit and a logic circuit to increase or decrease a duty ratio for an input clock and to perform a variable fine adjustment of the duty ratio by changing a delay time.
The means for varying a duty ratio of a clock signal, however, is not limited to the means disclosed in the prior art references above. Desirably, the duty ratio of the clock signal can be set flexibly in accordance with the scale or characteristics of the circuit receiving the clock signal.